1. Field of the Invention
The present invention generally relates to methods for determining signal delays in integrated circuits and, more particularly, to methods for determining signal delays in integrated circuits where the delays are due to the resistance of interconnecting wires.
2. State of the Art
During the design of integrated circuits, it is often necessary for design engineers to determine signal delays within the circuits. Although the signal delays could be determined by testing prototype circuits, integrated circuits are expensive and time consuming to fabricate in limited quantities. Accordingly, it is highly desirable to determine signal delays within integrated circuits by mathematical modeling techniques.
Signal delays in integrated circuits arise from various factors, including the resistance of wires that connect elements within the circuits. In fact, wire resistance becomes an increasingly significant factor in causing delays as integrated circuits become denser (i.e., contain increased numbers of elements per unit area) and as wire widths become narrower. In practice, however, it is difficult to calculate signal delays caused by wire resistances. Moreover, to be of practical use to circuit designers, the computational technique must be capable of computing all interconnect delays in integrated circuits having on the order of 100,000 or more transistors on a desk-top work station within a time frame on the order of, for example, one hour or less.
In practice, computer-based simulations of integrated circuits are often used for estimating signal delays. In one common method of circuit simulation, a computer program is used for numerically solving a system of non-linear differential equations derived from the state equations that describe the components of an integrated circuit undergoing design. However, this type of simulation program requires too much computational time and data storage capacity to be suitable for routine analysis of most integrated circuits of the LSI and VLSI class.
A technique called "macro-modelling" has also been used for simulating LSI and VLSI integrated circuits. In the macro-modeling technique, an integrated circuit is modelled as a number of "standard" blocks (i.e., macro-cells), whose electrical characteristics have been pre-characterized (usually, by circuit simulation). For example, one of the blocks in a macro-modelled circuit might be a NAND gate, and the pre-characterization of that block might provide a simple rule for calculating the delay at the gate output as a function of the capacitance being driven and the signals arriving at gate input pins. Then, using the predetermined rule, a logic simulator or timing verifier can predict the delay through the NAND gate in a macro-modelled integrated circuit. However, in conventional practice, such logic simulators do not account for the resistance of interconnecting wires in simulated circuits.